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Hierarchy of the DRAM Subsystem

Every channel has its own memory controller that means it has its own address, command, and data bus.

In a rank, the address and command bus are shared to all chips, but the data bus is dedicated to a chip. Therefore the rank can offer a wide interface.

In a chip, all of the address, command, and data bus are shared to banks. However, in each bank, the address, command, and data are latched, and each bank operates its own command.

A column can be accessed when a row is open(activated).

DRAM Operation

DRAM Operation starts with row activation. Activating a row means select and open a row of DRAM cells in a specific bank and then the data could be accessed through row buffer(which is also called sense amplifier) in size of a column. When accessing a row is finished then, the row should be precharged(closed) for activating another row. 

The most critical timing parameters of DRAM are tRCD, tCL, tRP. tRCD stands for RAS to CAS delay time which means activating a row is finished and the row is ready to read or write, after tRCD from the ACT(Activation) command. Once RD(Read) or WR(Write) command, data could be transferred after tCL. And when accessing a row is finished, the PRE(Precharge) command should be followed. Precharging a row takes tRP. 

Because the row address is transferred with ACT command and the column address is transferred with RD/WR, which means that row and column address are not used simultaneously, address pins could be shared. 

DRAM Bank Structure

DRAM Bank is a set of rows and columns, which operates a command. A DRAM chip consists of multiple banks, and each bank could operate its own command. However, the command, address, data pins are shared to all of the banks, and all of DRAM commands are synchronized, DRAM operations could be pipelined. With pipelining, bank structure is good for hiding long latency of DRAM(tRCD, tCL, tRP, etc).

This is a logical structure of a DRAM Bank. All of the pin counts are referenced from Micron DDR4 8Gb X8 DRAM Chip. In this case, a DRAM bank consists of 64K rows and 1K columns. This chip has 8 bit of data pin, generally, 8 of chips are combined into a DIMM. With 8 chips, each of 8 data pins, and 8 burst length, 64Byte of data could be read or write at single DRAM command. Row buffer size is 8Kb for each chip. 

This is a functional block diagram from Micron DDR4 8Gb X8 DRAM chip. Note that it is a chip. Because DDR4 uses 8 burst length, it seems that 64 bit of data in the row buffer could be transferred to FIFO, in a operation. The LSB 3 bits of column address are discarded, and 8 columns, each of 8 bits are accessed at once.