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There are various kinds of synthesis and implementation strategies in Xilinx Vivado.

When you have timing violations with your own codes, which you can check with the timing report, you need to modify your own codes to shorten the critical paths. However the timing violation came from the IPs which are already proven, you can use other synthesis and implemenation strategies.

Different strategies makes different timing, area, and power

Someone gives an example.(https://miscircuitos.com/vivado-synthesis-and-implementation-strategies/)

Below table shows my case. I cannot test for all of strategies, because it consumes so many time.

It seems that synthesis strategy make very few changes with my design.

There is no a absolute winner of synthesis and implementation strategy. You need to use various strategies but it may need some time, computing power and storages. In my case, I ran 8 synthesis strategies and 19 implementation strategies for each of synthesis. It takes about 2 days with 24 parallel processing on total 56 thread intel CPU, and it releases 96GB of data.

When you need to check the execution time in Xilinx SDK,

you can use below code.

Note that the timer should be enabled

#include <stdio.h>
#include "xtime_l.h"

int main(void){
	XTime t;
    
    XTime_StartTimer(); //enable timer
    
    XTime_GetTime(&t);
    printf("t = %lf\n", (double)t/COUNTS_PER_SECOND);
    
    return 0;
}

When you are using Xilinx SDK, you have to distinguish pointer and array. If you declare a variable as a pointer, you have to use it as a pointer not array. If a pointer is used as array, synchoronous interrupt handler(exception) may occur.

volatile unsigned int* mem;

for(i=0; i<SIZE; i++){
	mem[i] = i; //Synchoronous Interrupt Handler(exception) may occur
    //you have to use like this
    //*(mem+i) = i;
}

When you are using very large concatenated signals in Vivado simulation, it may cause elaborate step failure. You can release this problem with breaking into several smaller signals.

AR# 62969 says it may be fixed in 2015.1 version, however, it still exists in 2017.2 version

www.xilinx.com/support/answers/62969.html

When you get [Opt 31-67] Problem from running Vivado opt_design phase, you have to check all the related input/output pins. If one of your input/output pins is not connected, it can occur. And also, even if you connect all the input/output pins, it can occur with a non-driving output pin.

Because the original SODIMM from Micron no longer produced, the newer ZCU102 boards have changed SODIMM (You can find this issue from Xilinx AR#71961).

If you have ZCU102 Evaluation board labeled as 0432055-05 and you are using some old version of Vivado, you may have to change some parameters from either of followings:

1. Change in each Vivado project

You can change some DRAM parameters from block design - Zynq Ultrascale+ MPSoC - DDR Controller

2. Change in board preset

You can find a board preset file from <Xilinx install directory>/Vivado/<version>/data/boards/board_files/zcu102/<board_version>/preset.xml

Among so many parameters, you have to change 4 parameters: 

PSU__DDRC__DRAM_WIDTH 8 Bits -> 16 Bits

PSU__DDRC__DEVICE_CAPACITY 4096 MBits -> 8192 MBits

PSU__DDRC__BG_ADDR_COUNT 2 -> 1

PSU__DDRC__ROW_ADDR_COUNT 15 -> 16

If you have changed the board preset, you don't have to change from your Vivado project. You can just use auto preset.

You can use a raspberry pi for a remote UART terminal

The instructions are as followed:

1. Set up the Rasberry pi

 - OS: Raspbian

 - apps: openssh-server, screen

# sudo apt-get install -y openssh-server screen

2. Install USB-UART driver

 - Download linux source from https://www.silabs.com/developers/usb-to-uart-bridge-vcp-drivers

 Download Linux 3.x.x/4.x.x VCP Driver. You may need to sign up.

※ Raspberry pi kernel version is 5.4.79-v7+(2020.12.18), but it works!

 - Unzip the downloaded source

 - Compile

 You may need the kernel source. You can use rpi-source(github.com/notro/rpi-source/wiki)

# cd <unzip dir>
# sudo apt-get install git bc bison flex libssl-dev
# sudo wget https://raw.githubusercontent.com/notro/rpi-source/master/rpi-source -O /usr/local/bin/rpi-source
# sudo chmod +x /usr/local/bin/rpi-source
# rpi-source
# make

 - Install module

# sudo cp cp210x.ko /lib/modules/`uname -r`/kernel/drivers/usb/serial
# sudo insmod /lib/modules/`uname -r`/kernel/drivers/usb/serial/usbserial.ko
# sudo insmod cp210x.ko

3. Connect FPGA borad's UART and Raspberry pi's USB

4. Remote access to the RapberryPI

5. Use terminal

# sudo screen /dev/ttyUSB0 115200

When you are using multi-version of Xilinx hardware servers on a computer, you may find out some conflicts:

1. port conflict

The default port for the Xilinx hardware server is 3121. If two versions of hardware server working on a computer, the ports have to be different

In this case, you can use -stcp::<port> argument to change the port number

hw_server.bat -S -stcp::3122

2. XVC(Xilinx Virtual Cable) conflict

If one hardware server is working for a device, then the other hardware server doesn't work for another device. It is because the first one uses two devices even if one of them is not necessary. 

Therefore you need to map the server and device.

For this, the cable id is needed. you can use -e "set jtag-port-filter <cable_id>" argument to filter specific cable

hw_server.bat -e "set jtag-port-filter Xilinx/TUL/1234-tulA"