쵸코아몬드의 블로그

FPGA 같은 하드웨어를 사용하다보면, 가끔 데이터가 꼬일 때, Endianness 문제일 까 싶을 때가 있다.

간단한 C 코드를 통해 System의 Endianness 를 확인 할 수 있다.

예 1) 전처리기 활용

#if __BYTE_ORDER == __LITTLE_ENDIAN
	printf("Little Endian\n");
#elif __BYTE_ORDER == __BIG_ENDIAN
	printf("Big Endian\n");

예 2) Pointer 활용

int x = 1;
char* cp = &x;

if(*cp == 1){
	printf("Little Endian\n");
}
else{
	printf("Big Endian\n");
}

Hierarchy of the DRAM Subsystem

Every channel has its own memory controller that means it has its own address, command, and data bus.

In a rank, the address and command bus are shared to all chips, but the data bus is dedicated to a chip. Therefore the rank can offer a wide interface.

In a chip, all of the address, command, and data bus are shared to banks. However, in each bank, the address, command, and data are latched, and each bank operates its own command.

A column can be accessed when a row is open(activated).

DRAM Operation

DRAM Operation starts with row activation. Activating a row means select and open a row of DRAM cells in a specific bank and then the data could be accessed through row buffer(which is also called sense amplifier) in size of a column. When accessing a row is finished then, the row should be precharged(closed) for activating another row. 

The most critical timing parameters of DRAM are tRCD, tCL, tRP. tRCD stands for RAS to CAS delay time which means activating a row is finished and the row is ready to read or write, after tRCD from the ACT(Activation) command. Once RD(Read) or WR(Write) command, data could be transferred after tCL. And when accessing a row is finished, the PRE(Precharge) command should be followed. Precharging a row takes tRP. 

Because the row address is transferred with ACT command and the column address is transferred with RD/WR, which means that row and column address are not used simultaneously, address pins could be shared. 

DRAM Bank Structure

DRAM Bank is a set of rows and columns, which operates a command. A DRAM chip consists of multiple banks, and each bank could operate its own command. However, the command, address, data pins are shared to all of the banks, and all of DRAM commands are synchronized, DRAM operations could be pipelined. With pipelining, bank structure is good for hiding long latency of DRAM(tRCD, tCL, tRP, etc).

This is a logical structure of a DRAM Bank. All of the pin counts are referenced from Micron DDR4 8Gb X8 DRAM Chip. In this case, a DRAM bank consists of 64K rows and 1K columns. This chip has 8 bit of data pin, generally, 8 of chips are combined into a DIMM. With 8 chips, each of 8 data pins, and 8 burst length, 64Byte of data could be read or write at single DRAM command. Row buffer size is 8Kb for each chip. 

This is a functional block diagram from Micron DDR4 8Gb X8 DRAM chip. Note that it is a chip. Because DDR4 uses 8 burst length, it seems that 64 bit of data in the row buffer could be transferred to FIFO, in a operation. The LSB 3 bits of column address are discarded, and 8 columns, each of 8 bits are accessed at once.

일반적인 Linux 배포판을 쓰지 않고, Kernel source와 Root file system 으로 부터 Linux system 을 구성한 경우,

Linux runtime 에 kernel module을 compile 하여 insmod/rmmod 를 할 수 있다.

Kernel module을 컴파일 하기 위해서는 현재 Linux system 에서 사용되고 있는 kernel source를 필요로 한다.

일반적인 방법과 유사하게 사용하기 위해

kernel source 를 /usr/src 디렉토리에 위치시키고,

/lib/modules/<kernel_version>/build 와 symbolic link 시킨다.

커널 모듈을 컴파일 하기 위한 준비 작업은 아래 와 같다.

※ 참조: http://www.fun25.co.kr/blog/linux-ubuntu-14-04-kernel-module-compile

kernel module을 컴파일 할 Makefile은 아래와 같이 구성한다.

아래는 테스트를 위한 기본적인 kernel module source code.

kernel module을 컴파일 하고, insmod/rmmod 를 통해 test 한다.

※ 이 때, 현재 Linux system 에서 사용되는 kernel 과 다른 source로 부터 kernel module을 컴파일 하게 되면 version 차이로 오류가 나타난다.