Vivado synthesis and implementation strategies

There are various kinds of synthesis and implementation strategies in Xilinx Vivado.

When you have timing violations with your own codes, which you can check with the timing report, you need to modify your own codes to shorten the critical paths. However the timing violation came from the IPs which are already proven, you can use other synthesis and implemenation strategies.

 

Different strategies makes different timing, area, and power

Someone gives an example.(https://miscircuitos.com/vivado-synthesis-and-implementation-strategies/)

 

Below table shows my case. I cannot test for all of strategies, because it consumes so many time.

It seems that synthesis strategy make very few changes with my design.

 

There is no a absolute winner of synthesis and implementation strategy. You need to use various strategies but it may need some time, computing power and storages. In my case, I ran 8 synthesis strategies and 19 implementation strategies for each of synthesis. It takes about 2 days with 24 parallel processing on total 56 thread intel CPU, and it releases 96GB of data.